The present invention relates to the design of multilayer filter capacitors made of a dielectric material such as a ceramic dielectric material. A capacitor is an electronic component that stores electrical energy in the form of an electric field, and is commonly used for filtering and energy storage applications in electronic circuits. The electric field forms between electrically opposed electrodes when a voltage is applied to the capacitor terminals. An ideal capacitor is characterized by the equation:i=C×dv(t)/dt 
where i is the current flowing through the capacitor, C is the capacitance of the capacitor in farads, and v(t) is the voltage across the capacitor with respect to time.
Because the current flowing through a capacitor depends on the rate at which the voltage across its terminals changes (i.e. the value of dv(t)/dt), the impedance of a capacitor varies inversely with frequency. This makes capacitors useful as signal filters. Realizable capacitors deviate from this ideal relationship due to series resistance and series inductance, which are unavoidable byproducts of the physical configuration of the capacitor as well as the properties of the materials used to make the capacitor. At lower frequencies, the impedance of a filter capacitor is dominated by the capacitive element. However, as operational frequencies increase, the equivalent series resistance and equivalent series inductance begin to dominate the device impedance, which limits useful bandwidth of the capacitor.
One type of capacitor in common use is a multilayer capacitor. A multilayer capacitor is configured with multiple conducting plates separated from each other by layers of dielectric material. A type of multilayer capacitor commonly available is configured so that metal plate regions of alternating polarity are stacked in such a way that the metal plate regions are in a parallel relationship and at least partially overlap each other, with the overlapping regions providing capacitance in a manner that may be modeled as a capacitor with two parallel plate electrodes. The capacitance of the conventional overlapping parallel-plate capacitor is approximated by the formula:C=kA/d 
where C is the capacitance in farads, k is the dielectric constant in farads per meter, A is the area of electrode overlap in square meters, and d is the distance of separation between plates in meters. To obtain the minimal physical size for a capacitor with a given capacitance, it is desirable to minimize d to increase capacitance per unit volume. However, there is a minimum value of d which will allow the capacitor to operate at its rated voltage without the dielectric breaking down. Conversely, as the required operating voltage of the capacitor increases, d must also increase. Typically, this causes the maximum capacitance achievable within a fixed capacitor package size to drop in roughly inverse proportion to the square of the maximum rated voltage of the capacitor.
FIGS. 1A and 1B give an example of a known multilayer, discoidal, feed-through type ceramic filter capacitor 1 of the type previously described. The capacitor 1 has a central hole, or bore, that includes a first conductive metal surface forming an inner terminal 11, and external rim surface, or circumference, which includes a second conductive metal surface forming an outer terminal 12. The capacitor 1 is substantially comprised of multiple ceramic layers 13 x that form a ceramic laminate body 13. Between the layers 13 x are a number of ring-shaped first metalized areas, or electrode plates 14 x, that collectively form a first electrode 14, and a number of ring-shaped second metalized areas, or electrode plates 15 x, that collectively form a second electrode 15.
A typical discoidal feed-through capacitor 1 may have an external diameter D of about 0.105 inch (“in.”) or 105 mils; an internal diameter d of about 35 mils; and the overall thickness T of about 65 mils. Further, a typical ceramic dielectric has a voltage rating of about 100 volts per mil (0.001 in) of thickness, so if the capacitor 1 is designed to have a voltage rating of about 1000 volts, it will require a ceramic dielectric thickness tin the axial direction between adjacent electrode plates 14 x, 15 x of about 10 mils. Because a voltage breakdown is more likely to occur along the imperfections in the seams 16 between layers 13 x than through layers 13 x, the radial separation d1 between electrode plates 14 x, 15 x and the external metallization layers forming the capacitor terminals 11, 12 should be at least 50% greater than the plate separation in the axial direction across the layers 13 x. Thus, the distance d1 for the capacitor 1 should be about 15 mils.
The internal design of the capacitor 1 is shown in FIG. 1B, which presents a cross-sectional view. As discussed, the thickness t of the dielectric is 10 mils layer-to-layer, with an end margin d1 between electrodes 14, 15 and capacitor terminals 11, 12 of 15 mils. The top and bottom ceramic cover layers are typically 7.5 mils thick, resulting in an overall thickness of the laminate body 13 of about 65 mils. Given a desired electrode separation of 10 mils, this allows three internal electrode plates 14 x, 15 x of each polarity, giving five active electrostatic field regions with a total overlapping area A (i.e. −effective electrode area) of 0.005498 sq. in., or 5×π×((0.0375 in)2−(0.0325 in)2).
FIGS. 2A and 2B give an example of a known multilayer, discoidal, feed-through type ceramic filter capacitor 2 disclosed in U.S. Pat. No. 6,619,763 (issued Sep. 16, 2003), which is incorporated herein by reference. Capacitor 2 relies on the fringe-effect capacitance between non-overlapping electrodes rather than the parallel plate capacitance between overlapping electrodes as in capacitor 1. Although not shown here, for a capacitor 2 having substantially identical outer physical dimensions as capacitor 1, the number of electrode plates 24 x, 25 x is typically much greater than the number of electrode plates 14 x, 15 x in capacitor 1. Since the axially adjacent electrodes plates 24 x are all attached to the outer capacitor terminal 27, and the axially adjacent electrode plates 25x are all attached to the inner capacitor terminal 26, the electric field across the dielectric layers 23 x between the electrode plates 24 x, 25 x in the axial direction is greatly reduced. This allows adjacent electrodes 24 x, 25 x to be stacked more closely than in capacitor 1, resulting in an increased number of relatively thinner ceramic layers 23 x, which comprise the laminate body 23. The result is that the combined plates 24 x and 25 x act as nearly continuous, axially extending electrodes 24, 25 respectively. The effective electrode area (A) of the capacitor is thus approximated by the area of the electrically active surface the inner electrode 25, which is h×2π×r, where h is the height of the electrode stack and r is the radius of the vertical surface of inner electrode 25. Using similar design parameters as in the previous example results in capacitor 2 having an effective electrode area of 0.009503 sq. in., or (0.055 in)×2π×(0.0275 in), which is nearly twice the effective electrode area of capacitor 1.
FIG. 2C shows a cross-sectional view of another known multilayer discoidal feed-through capacitor 3 disclosed in U.S. Pat. No. 6,619,763. Like capacitor 2, capacitor 3 relies on fringe-effect capacitance between non-overlapping electrodes. However, in capacitor 3 opposing plates 34 x, 35 x are positioned on alternating dielectric layer 23 x laminate seams 28 x. In capacitor 2, the seams 28 x between dielectric layers 23 x of the laminate body 23 extend between the electrode plates 24 x, 25 x. Due to imperfections in the lamination boundary forming seam 28 x, a voltage breakdown path along a seam 28 x typically occurs at relatively lower electrostatic field strength than a path that passes through a dielectric layer 23 x. Therefore, the voltage rating of capacitor 2 is typically limited by a voltage breakdown that occurs between opposing electrode plates 24 x, 25 x along the seams 28 x. Referring to FIG. 2C, the capacitor 3 has opposite polarity electrode plates 34 x, 35 x on alternating dielectric layers 23 x of the laminate body 23. Capacitor 3 thus requires that a voltage breakdown path pass through a dielectric layer 23 x to allow an arc 39 between opposite polarity electrode plates 34 x, 35 x. Such a failure path typically requires a substantially higher voltage than a path along a seam 28 x for similarly spaced electrode plates. Capacitor 3 therefore typically offers increased breakdown voltage without significantly altering the effective electrode area.
FIGS. 3A and 3B give an example of a known multilayer ceramic chip capacitor 4. The capacitor 4 is formed essentially in the shape of a parallelepiped so that it will lay flat on a circuit board and to facilitate automated circuit board assembly. Capacitor 4 includes capacitor terminals 41, 42 and is substantially comprised of multiple ceramic layers 43 x that form a ceramic laminate body 43. Between the layers 43 x are a number of first metalized areas, or electrode plates, 44 x that collectively form a first electrode 44, and a number of second metalized areas, or electrode plates, 45 x that collectively form a second electrode 45. The parallel plates 44 x, 45 x are connected by the metalized layers on the ends of the laminate body 43 that form the capacitor terminals 41, 42. Multilayer chip capacitors come in numerous sizes, with smaller packages being developed on an ongoing basis. Typical chips available today may range in size from 10 mils long by 5 mils wide (commonly referred to in the industry as a 01005 size capacitor), to 500 mils long by 300 mils wide (or 5030 size capacitor) and beyond, with larger sized chips typically allowing for a higher capacitance at any given voltage rating. One example of a typical surface mount ceramic chip capacitor 4 may have an external length L of about 80 mils; an external width W of 50 mils; and the overall thickness T of 30 mils. Using the same design parameters as with the discoidal capacitor 1 in FIGS. 1A-1B, a multilayer chip capacitor 4 designed to have a rated voltage of 1000 volts will require a ceramic dielectric thickness t between adjacent plates 44 x, 45 x of about 10 mils. Likewise, the longitudinal separation d1 between electrode plates 44 x, 45 x and the terminals 41, 42 will be about 15 mils. Top and bottom ceramic cover layers are typically 5 mils thick, resulting in an overall thickness of the laminate body 43 for the capacitor 4 with three total electrode plates 44 x, 45 x, of about 30 mils. Two active electrostatic field regions result in an overlapping area A (i.e. −effective electrode area) of 0.005 sq. in., or 2×(0.08−0.03)×0.05 in., which is about 90% of the electrode surface area as in capacitor 1.
Because of the 15 mil horizontal spacing required to maintain the 1000 volt rating in our example, if the dimensions of capacitor 3 are reduced to an external length L of about 60 mils; an external width W of about 30 mils; and keeping the overall thickness T of about 30 mils (known in the industry as a 0603 sized capacitor), the electrode area shrinks to about 0.0018 sq. in., or 2×(0.06−0.03)×0.03 in., which is only 33% of the electrode surface area as in capacitor 1. As can be seen, because of the required electrode spacing, it becomes very difficult to maintain high voltage ratings with conventional designs in a multilayer chip capacitor as the exterior dimensions shrink.
High voltage capacitors have multiple applications, but are of particular use in filtering electrical signals on the wires and leads of implanted cardiac pacemakers and cardiac defibrillators. Cardiac defibrillators in particular use high voltages, commonly about 750 volts. When the electrodes of a filter capacitor are subjected to these high voltages, which with safety margins may be thousands of volts, capacitors having partially overlapping electrode plates are subject to developing voltage breakdown paths. Such paths can occur between adjacent plates through the ceramic, or to oppositely-charged regions of the outside surface of the capacitor where electrical connections are made. Due to the large electrode plate separations required to prevent this voltage breakdown, high voltage capacitors having high capacitive values are difficult to produce in a small form factor, particularly in the case of multilayer chip capacitors. Discoidal feed-through capacitors, on the other hand, have been found to be prone to cracking when used in implanted cardiac pacemakers because the metal wire travels though the center of the capacitor. Discoidal feed-through capacitors also have an inconvenient form factor as compared to chip capacitors. Thus, medical device manufactures in particular have a need for chip capacitors having high voltage ratings coupled with capacitances at least as high as existing discoidal feed-through capacitors.
Accordingly, there is a need for improved multilayer chip capacitors of substantially the same size as currently available, as well as in smaller packages, that provide greater capacitance while at the same time having substantially higher breakdown voltages. At the same time, there is a need for these same capacitors to have lower series resistances and inductances so as to provide better filtering of the high frequency interferences frequently encountered in our modern wireless world.